1. Field of the Invention
This invention relates to methods of analyzing I/O cell layouts for integrated circuits, where the layout includes a location and type for each I/O cell used in the integrated circuit. More specifically, this invention relates to methods of analyzing a proposed I/O cell layout at an early stage in the design of an integrated circuit to determine whether the relative arrangement of the I/O cells and the particular types of I/O cells chosen for the layout will meet design goals with respect to power bus voltage drop, electromigration and noise limits.
2. Description of Related Art
To reduce cost and speed design, integrated circuits, such as custom logic application specific integrated circuits (ASIC) chips, are usually constructed from standard elements. These elements include such items as the die size for the silicon chip, the packaging, and the input/output (I/O) circuitry.
Typically, each I/O circuit is selected by the integrated circuit designer from a library of different types of standard I/O circuits that provide desirable I/O functions. Some I/O circuits in the library will be input only, some will be output only, some will provide both input and output functionality with various testing functions, etc. Each circuit is configured similarly with respect to common connection points, such as the location of the connections to power and ground. This arrangement allows any I/O circuit (referred to as an I/O cell) to be moved into any one of numerous standardized I/O cell placement locations on a standardized silicon die (referred to as a chip image).
At an early stage of ASIC design, the chip designer selects a particular chip image suitable for the circuit of interest. As an example, a family of popular chip images includes a variety of silicon chips of increasing die sizes, each chip being configured with wiring to supply ground and power connection to multiple I/O cell placement locations, all of which are located along the four edges surrounding the perimeter of the chip. Larger peripheral chip images have more available I/O cell placement locations where the standard I/O cells can be positioned.
One important consideration for the chip designer will be the selection of a large enough chip image to accommodate all the I/O cells needed for the ASIC to communicate with other off-chip system devices. A typical ASIC design may have from 200 to more than 1000 different I/O signals, each one requiring a corresponding I/O cell to handle its I/O signal.
The available I/O cell placement locations along the perimeter of the chip are all similar so that, in theory, almost any I/O cell can be positioned there. In practice, however, not all these locations are identical and there are limits to the placement of different types of I/O cells in the available locations. For example, some locations are farther from the power supply, and have a higher resistance connection to power and/or ground. This limits the current that I/O cells positioned here may draw. Another limit relates to test circuits which can be placed only in special test circuit I/O cell slots. There are other limits on placement needed to minimize electromigration and noise.
In the design of ASIC chips, the designer usually knows the input and output requirements of the chip long before the details of the internal ASIC chip circuitry are finalized. In peripheral chip image designs, each I/O cell is connected to a particular pin extending out of the ASIC chip. Thus, positioning the I/O cells controls the design of the circuit board that the chip will be installed into. The circuit board must bring the proper input and output signals to the correct pin.
Often, the assignment of the I/O cells to their location is done very early so that related design of the circuitry connected to the ASIC can be done. Any changes made late in the design process to this early proposed I/O cell layout increases cost. It is important to be able to determine as early as possible whether the proposed layout for the I/O cells will meet all design goals.
Although the discussion above describes peripheral chip designs, in other designs, I/O cells may be placed at interior locations of the chip. Also, for any particular die, whether it provides peripheral I/O placement locations only, or permits interior I/O cell placement, there may be different packages into which the silicon chip may be mounted. The packaging may also put limits on the placement of the I/O cells on the silicon die. Throughout the discussion below the term xe2x80x9cchip imagexe2x80x9d will be used to generally refer to this combination of a silicon die and packaging for that die. The chip image determines the limits on the placement of I/O cells on the silicon die and package combination.
An integrated circuit process technology has scaled down to smaller and smaller dimensions, particularly in the 0.25 micron size and smaller, resistance has increased in the chip power distribution network, resulting in higher IR voltage drops throughout. ASIC chip I/O counts per die have also been increasing. With more I/O cells switching, total noise increases and it has become significantly more difficult to place I/O cells in a proposed I/O cell layout that is workable. Chip voltages have also been decreasing producing lower noise margins. The increasing complexity of the on chip metal wiring has made manual IR drop calculations difficult, while the increasing frequencies of ASIC chips has made it important to decrease noise.
Although most ASIC designs are given a very comprehensive analysis of timing, test coverage, DRC and LVS, the electrical analysis of the power bus is very limited in scope. Some ASIC designs continue to fail for reasons not predicted before the design is manufactured due to the limited scope of the power bus analysis. Some of these failures have been traced to power supply compression resulting from resistive IR voltage drop and inductive di/dt noise caused by switching high speed I/Os. When power supply compression occurs it manifests itself as timing problems or functional failure caused by false switching.
The variety of die sizes and packages available for ASICs make it difficult to provide general I/O placement and electrical checking guidelines. A contributing problem is the desirability of freezing I/O cell assignments early in the design cycle to allow for the manufacturing lead time of cards or modules intended to receive the ASIC chip. As a result, I/O cell placement has heretofore been a manual process completed early in the design without significant electrical checking.
Designers have typically done this manual check based only on general noise and electromigration design guidelines. Detailed noise analysis with tools such as ASX or H-SPICE simulation has been possible, but this is a long process involving hard work and has either been done late in the design cycle or not at all.
Problems identified late in the design cycle require extensive rework including I/O cell placement changes, substituting high power I/O cells with lower power I/O cells, chip floorplanning, layout, timing and checking, all of which increases cost.
Power and ground bus electromigration checking has also typically been done manually. To shorten the time required for this activity, analysis has been done only for small areas which were thought to represent the areas of worst case electromigration. While this shortened the time required for analysis it often missed problem areas and it lacked accuracy. Power and ground bus IR drop checking was seldom done due to its complexity.
Although prior art extraction tools for doing IR voltage drop analysis and EM analysis are available, such tools can only be used late in the design process when the repair of errors is more difficult and costly. Extraction analysis is also a relatively lengthy and expensive process.
It would, therefore, be a distinct advantage to have a method and apparatus that could provide a method of analyzing I/O cell layouts for integrated circuits that can be completed quickly and easily at an early stage in the design process. It would be further advantageous if the method and apparatus could provide a simplified method of analyzing I/O cell layouts for power and ground bus IR drop problems, as well as noise and electromigration problems. The present invention provides such a method and apparatus.
In one aspect, the present invention is a method of analyzing I/O cell layouts for integrated circuits that starts with the step of providing data defining a proposed I/O cell layout for a plurality of I/O cells, the data including a selected chip image. The chip image is selected by a designer to accommodate the proposed I/O cell layout. The data includes a specified I/O cell type and a specified I/O cell location for each I/O cell used in the proposed I/O cell layout. The method also includes the steps of providing a set of limit rules for the selected chip image, the limit rules defining limits on the layout of I/O cells on the selected chip image, providing characteristics for each I/O cell type used in the proposed I/O cell layout, checking the proposed I/O cell layout by applying the data defining the proposed I/O cell layout and the characteristics for each I/O cell type used in the proposed I/O cell layout to the limit rules for the selected chip image, and reporting all I/O cells used in the proposed I/O cell layout that do not meet the limit rules for the selected chip image.
In the preferred embodiment, the method of analyzing I/O cell layouts for integrated circuits includes selecting the chip image from among a plurality of available chip images and the proposed I/O cell layout includes I/O cells selected from among a plurality of available I/O cells suitable for use on the selected chip image. The step of providing a set of limit rules for the selected chip image preferably comprises selecting the set of limit rules for the selected chip image from among a plurality of sets of limit rules previously prepared for the plurality of available chip images.
In the step of providing characteristics for each I/O cell type used in the proposed I/O cell layout the characteristics for each I/O cell type are selected from among a plurality of characteristics previously determined for the plurality of available I/O cells.
In the step of providing data defining a proposed I/O cell layout, the data may include data defining duty cycle, switching factor, loading data, termination data, chip operating temperature and desired chip lifetime data.
The step of reporting all I/O cells used in the proposed I/O cell layout that do not meet the limit rules for the selected chip image may be performed by providing a text file report. However, in the most highly preferred embodiment of the invention, the reporting step includes providing a graphical image of the proposed I/O cell layout for the selected chip image with the cells used in the proposed I/O cell layout that do not meet the limit rules for the selected chip image being marked in the graphical image, preferably by highlighting in color.
The method of the present invention may also include the steps of modifying the proposed layout to meet the limit rules, checking the modified proposed I/O cell layout by applying the data defining the modified proposed I/O cell layout and the characteristics for each I/O cell type used in the modified proposed I/O cell layout to the limit rules for the selected chip image, and revising the graphical image to mark only I/O cells used in the modified proposed I/O cell layout that do not meet the limit rules for the selected chip image.
One aspect of the method of analyzing I/O cell layouts includes providing IR limits in the set of limit rules and the step of checking the proposed I/O cell layout includes power bus IR voltage drop limit checking. Another aspect of the method of analyzing I/O cell layouts includes providing electromigration limits in the set of limit rules and the step of checking the proposed I/O cell layout includes electromigration limit checking. Still another aspect of the method of analyzing I/O cell layouts includes providing di/dt limits in the set of limit rules and the step of checking the proposed I/O cell layout includes di/dt noise limit checking.